Altera cyclone V Technical Reference page 2228

18-138
hcchar0
Bit
1
PrtConnDet
0
prtconnsts
hcchar0
Channel_number: 0.
Module Instance
usb0
usb1
Offset:
0x500
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30 29
chena chdis Reser
ved
RO RO
0x0 0x0
15 14 13
epdir epnum
RW RW 0x0
0x0
Altera Corporation
Name
The core sets this bit when a device connection is
detected to trigger an interrupt to the application
using the Host Port Interrupt bit of the Core Interrupt
register (GINTSTS.PrtInt)​. This bit can be set only by
the core and the application should write 1 to clear
it.The application must write a 1 to this bit to clear the
interrupt.
Value
0x0
0x1
Defines whether port is attached.
Value
0x0
0x1
Base Address
0xFFB00000
0xFFB40000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
28 27 26 25
devaddr
RW 0x0
12 11 10 9
Description
Description
Device connection detected
No device connection detected
Description
No device is attached to the port
A device is attached to the port
0xFFB00500
0xFFB40500
Bit Fields
24 23 22 21
8 7 6 5
RW 0x0
Access
Register Address
20 19 18
ec eptype
RW 0x0 RW 0x0
4 3 2
mps
USB 2.0 OTG Controller
cv_5v4
2016.10.28
Reset
RO 0x0
RO 0x0
17 16
lspdd Reserved
ev
RW
0x0
1 0
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