Altera cyclone V Technical Reference page 2173

cv_5v4
2016.10.28
Module Instance
usb0
usb1
Offset:
0x34
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
disulpid Reserved
rvr
RO 0x0
15 14
gpvndctl Fields
Bit
31
disulpidrvr
27
vstsdone
USB 2.0 OTG Controller
Send Feedback
0xFFB00000
0xFFB40000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
vstsd vstsb
one sy
RO RO
0x0 0x0
13 12 11 10
vctrl
RW 0x0
Name
The application sets this bit when it has finished
processing the ULPI Carkit Interrupt
(GINTSTS.ULPICKINT). When Set, the otg core
disables drivers for output signals and masks input
signal for the ULPI interface. otg clears this bit before
enabling the ULPI interface.
Value
0x0
0x1
The core sets this bit when the vendor control access
isdone. This bit is cleared by the core when the
application sets the New Register Request bit (bit 25).
Value
0x0
0x1
Base Address
Bit Fields
25 24 23 22
newre Reserved regwr
greq
RW
RW 0x0
0x0
9 8 7 6
Description
Description
ULPI ouput signals
Disable ULPI ouput signals
Description
VStatus Done inactive
VStatus Done active
gpvndctl
Register Address
0xFFB00034
0xFFB40034
21 20 19 18
regaddr
RW 0x0
5 4 3 2
regdata
RW 0x0
Access
RO
RO
18-83
17 16
1 0
Reset
0x0
0x0
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