Altera cyclone V Technical Reference page 2125

cv_5v4
2016.10.28
Register
doepdma15 on page 18-
836
doepdmab15 on page
18-836
Power and Clock Gating Register
Register
pcgcctl on page 18-
837
USB Data FIFO Address Map
Name
EP0/HC0 FIFO
EP1/HC1 FIFO
EP2/HC2 FIFO
EP3/HC3 FIFO
EP4/HC4 FIFO
EP5/HC5 FIFO
USB 2.0 OTG Controller
Send Feedback
Offset Width Acces
0xCF4 32
0xCFC 32
Offset Width Acces
0xE00 32
Description
This address space is
allocated for Endpoint
0/Host Channel 0 push/
pop FIFO access.
This address space is
allocated for Endpoint
1/Host Channel 1 push/
pop FIFO access.
This address space is
allocated for Endpoint
2/Host Channel 2 push/
pop FIFO access.
This address space is
allocated for Endpoint
3/Host Channel 3 push/
pop FIFO access.
This address space is
allocated for Endpoint
4/Host Channel 4 push/
pop FIFO access.
This address space is
allocated for Endpoint
5/Host Channel 5 push/
pop FIFO access.
USB OTG Controller Module Registers Address Map
Reset Value
s
Device OUT Endpoint 15 DMA
RW 0x0
Address Register
Device OUT Endpoint 15 DMA
RO 0x0
Buffer Address Register
Reset Value
s
Power and Clock Gating Control
RW 0x0
Register
Start Address Offset
0x1000
0x2000
0x3000
0x4000
0x5000
0x6000
18-35
Description
Description
End Address Offset
0x1FFF
0x2FFF
0x3FFF
0x4FFF
0x5FFF
0x6FFF
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