Table 2-6 Trace Control Register - ARM ARM966E-S Technical Reference Manual

Programmer's Model
Register bit Meaning when written
31:21 Instruction SRAM BIST size
20 Reserved (should be zero)
19 Reserved (should be zero)
18 Instruction SRAM BIST enable
17 Instruction SRAM BIST pause
16 Instruction SRAM BIST start strobe
15:5 Data SRAM BIST size
4 Reserved (should be zero)
3 Reserved (should be zero)
2-10
Note
Opcode_1 is set HIGH when accessing Register 15. Opcode_2 is used to index registers
within the Register 15 register map.
Trace control register
The trace control register allows the masking of interrupts during trace. This register
allows nIRQ and nFIQ interrupt priority over FIFOFULL to be programmed.
Table 2-6 shows the bit assignments within the Trace control register.
BIST control register
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Register bit Content
0 Reserved (should be zero)
1 1 = Mask nIRQ interrupts during trace
0= Do not mask nIRQ interrupts during trace
2 1 = Mask nFIQ interrupts during trace
0 = Do not mask nFIQ interrupts during trace
31:3 Reserved (should be zero)
Meaning when read
Instruction SRAM BIST size
Instruction SRAM BIST complete flag
Instruction SRAM BIST fail flag
Instruction SRAM BIST enable
Instruction SRAM BIST pause
Instruction SRAM BIST running flag
Data SRAM BIST size
Data SRAM BIST complete flag
Data SRAM BIST fail flag

Table 2-6 Trace control register

Table 2-7 BIST control register
ARM DDI 0186A