Floating-Point Rounding Control Definitions; Floating-Point Computation Model Control Definitions - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

fields flags are merely indications of the occurrence of floating-point excep-
tions.
Flush-to-Zero (FTZ) mode causes results which encounter "tininess" (see
Tininess, Inexact and Underflow" on page
signed zero. Flush-to-Zero mode can be enabled only if Underflow is disabled. If
Underflow is enabled then it takes priority and Flush-to-Zero mode is ignored. Note that
the software exception handler could examine the Flush-to-Zero mode bit and choose
to emulate the Flush-to-Zero operation when an enabled Underflow exception arises.
The FPSR.sfx.u and FPSR.sfx.i bits will be set to 1 when a result is flushed to the
correctly signed zero because of Flush-to-Zero mode. If enabled, an inexact result
exception is signaled.
A floating-point result is rounded based on the instruction's.pc completer and the status
field's wre, pc, and rc control fields. The result's significand precision and exponent
range are determined as described in
Control Definitions" on page
rounding direction (see
Table 5-5.
FPSR.sfx.rc
Table 5-6.
Computation Model Control Fields
Instruction's.pc
Completer
.s
.d
.s
.d
none
none
none
none
none
none
none
none
not applicable
not applicable
a. For parallel FP instructions which have no.pc completer (e.g., fpma).
b. For non-parallel FP instructions which have no.pc completer (e.g., frcpa).
1:90
1:90. If the result isn't exact, FPSR.sfx.rc specifies the
Table 5-5).

Floating-point Rounding Control Definitions

Nearest
(or even)
00

Floating-point Computation Model Control Definitions

FPSR.sfx's FPSR.sfx's
Dynamic pc Dynamic wre
Field Field
ignored 0
ignored 0
ignored 1
ignored 1
00 0
01 0
10 0
11 0
00 1
01 1
10 1
11 1
a
ignored ignored
b
ignored ignored
1:106) to be truncated to the correctly
Table 5-6, "Floating-point Computation Model
- Infinity + Infinity
(down) (up)
01 10
Computation Model Selected
Significand Exponent
Precision Range
24 bits 8 bits
53 bits 11 bits
24 bits 17 bits
53 bits 17 bits
24 bits 15 bits
N.A. N.A.
53 bits 15 bits
64 bits 15 bits
24 bits 17 bits
N.A. N.A.
53 bits 17 bits
64 bits 17 bits
24 bits 8 bits
64 bits 17 bits
Volume 1, Part 1: Floating-point Programming Model
"Definition of
Zero
(truncate/chop)
11
Computational Style
IEEE real single
IEEE real double
Register format range,
single precision
Register format range,
double precision
IA-32 stack single
Reserved
IA-32 stack double
IA-32 double-extended
Register format range,
single precision
Reserved
Register format range,
double precision
Register format range,
double-extended precision
A pair of IEEE real singles
Register format range,
double-extended precision