Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 181

4.2.4.4 Case 3
Suppose the if-clause is executed 30% of the time and the branch mispredicts 30% of
the time. The average number of clocks for:
• Unpredicated code is:
(2 cycles * 30%) + (18 cycles * 70%) + (10 cycles * 30%) = 16.2 clocks
• Predicated code is:
(5 cycles * 30%) + (18 cycles * 70%) = 14.1 clocks
In this case, if-conversion would decrease the execution cost by more than two clocks,
on average.
4.2.4.5 Overlapping Resource Usage
Before performing if-conversion, the programmer must consider the execution
resources consumed by predicated blocks in addition to considering flow-dependency
height. The resource availability height of a set of instructions is the minimum number
of cycles taken considering only the execution resources required to execute them.
The code below is derived from an if-then-else statement. Given the generic machine
model that has only two load/store (M) units. If a compiler predicates and combines
these two blocks, then the resource availability height through the block will be four
clocks since that is the minimum amount of time necessary to issue eight memory
operations:
then_clause:
else_clause:
end_if:
As with the example in the previous section, assuming various misprediction rates and
taken branch penalties changes the decision as to when to predicate and when not to
predicate. One case is illustrated below.
4.2.4.6 Case 1
Suppose the branch condition mispredicts 10% of the time and that the predicated code
takes four clocks to execute. The average number of clocks for:
• Non-predicated code is: (10 cycles * 10%) + 2 cycles = 3 cycles
• Predicated code is: 4 cycles
Predicating this code would increase execution time even though the flow dependency
heights of the branch paths are equal.
1:170
ld r1=[r21] // Cycle 0
ld r2=[r22] // Cycle 0
st [r32]=r3 // Cycle 1
st [r33]=r4 ;; // Cycle 1
br end_if
ld r3=[r23] // Cycle 0
ld r4=[r24] // Cycle 0
st [r34]=r5 // Cycle 1
st [r35]=r6 ;; // Cycle 1
Volume 1, Part 2: Predication, Control Flow, and Instruction Stream