Overview; Non-Speculative Memory References; Stores To Memory; Loads From Memory - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

Memory Reference
3.1

Overview

Memory latency is a major factor in determining the performance of integer
applications. In order to help reduce the effects of memory latency, the Itanium
architecture explicitly supports software pipelining, large register files, and
compiler-controlled speculation. This chapter discusses features and optimizations
related to compiler-controlled speculation. See
Loop Support"
The early sections of this chapter review non-speculative load and store in the Itanium
architecture, and general concepts and terminology related to data dependencies. The
concept of speculation is then introduced, followed by discussions and examples of how
speculation is used. The remainder of this chapter describes several important
optimizations related to memory access and instruction scheduling.
3.2

Non-speculative Memory References

The Itanium architecture supports non-speculative loads and stores, as well as explicit
memory hint instructions.
3.2.1

Stores to Memory

Itanium integer store instructions can write either 1, 2, 4, or 8 bytes and 4, 8, or 10
bytes for floating-point stores. For example, a st4 instruction will write the first four
bytes of a register to memory.
Although the Itanium architecture uses a little endian memory byte order by default,
software can change the byte order by setting the big endian (be) bit of the user mask
(UM).
3.2.2

Loads from Memory

Itanium integer load instructions can read either 1, 2, 4, or 8 bytes from memory
depending on the type of load issued. Loads of 1, 2, or 4 bytes of data are
zero-extended to 64-bits prior to being written into their target registers.
Although loads are provided for various data types, the basic data type is the quadword
(8 bytes). Apart from a few exceptions, all integer operations are on quadword data.
This can be particularly important when dealing with signed integers and 32-bit
addresses, or any addresses that are shorter than 64 bits.
Volume 1, Part 2: Memory Reference
for a complete description of how to use software pipelining.
Chapter 5, "Software Pipelining and
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