Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 130

Table 6-2.
Field
av
ig
d/b
g
6.2.2.3.1
On the transition into IA-32 code, the IA-32 segment descriptor and selector registers
(GDT, LDT, DS, ES, CS, SS, FS and GS) must be initialized by Itanium
architecture-based code to the required values based on IA-32 and Itanium calling
conventions and the segmentation model used.
Itanium architecture-based code may manually load a descriptor with an 8-byte fetch
from the LDT/GDT, unscramble the descriptor and write the segment base, limit and
attribute. Alternately, Itanium architecture-based software can switch to the IA-32
instruction set and perform the required segment load with an IA-32 Mov Sreg
instruction. If Itanium architecture-based code explicitly loads the segment descriptors,
it is responsible for the integrity of the segment descriptor.
The processor does not ensure coherency between descriptors in memory and the
descriptor registers, nor does the processor set segment access bits in the LDT/GDT if
segment registers are loaded by Itanium instructions.
6.2.2.3.2
For IA-32 instruction set execution, most segment protection checks are applied by the
processor when the segment descriptor is loaded by IA-32 instructions into a segment
register. However, segment descriptor loads from the Itanium instruction set into the
general purpose register file perform no such protection checks, nor are segment
Access-bits updated by the processor.
If Itanium architecture-based software directly loads a descriptor, it is responsible for
the validity of the descriptor, and ensuring integrity of the IA-32 Protected Mode, Real
Mode or VM86 environments.
initial IA-32 environment. The processor checks the integrity of the IA-32 environment
as defined in
Volume 1, Part 1: IA-32 Application Execution Model in an Intel
IA-32 Segment Register Fields (Continued)
Bits
60 Ignored – This field is ignored by the processor during IA-32 instruction set execution.
This field is available for IA-32 software use and there will be no future use for this field.
For Itanium instructions, implementations which do not support the ld16, st16 and
cmp8xchg16 instructions can either ignore writes and return zero on reads, or write the
value and return the last value written on reads. Implementations which do support these
instructions write the value and return the last value written on reads.
61 Ignored – This field is ignored by the processor during IA-32 instruction set execution.
This field may have a future use and should be set to zero by IA-32 software. For Itanium
instructions, implementations which do not support the ld16, st16 and cmp8xchg16
instructions can either ignore writes and return zero on reads, or write the value and
return the last value written on reads. Implementations which do support these
instructions write the value and return the last value written on reads.
62 Segment Size. If 0, IA-32 instruction set effective addresses within the segment are
truncated to 16-bits. Otherwise, effective addresses are 32-bits. The code segment's
d/b-bit also controls the default operand size for IA-32 instructions. If 1, the default
operand size is 32-bits, otherwise 16-bits.
63 Segment Limit Granularity. If 1, scales the segment limit by lim=(lim<<12) | 0xFFF for
IA-32 instruction set memory references. This field is ignored for Intel
instruction set memory references.
Data and Code Segments
Segment Descriptor and Environment Integrity
Table 6-3
"IA-32 Environment Runtime Integrity Checks" on page
Description
defines software guidelines for establishing the
® ®
Itanium System Environment
® ®
Itanium
1:122. On the
1:119