Using Intel ® Itanium ® Instructions; Format; Expressing Parallelism - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

There are 64, one-bit predicate registers (
of instructions and conditional branches. The first register,
reads true (1). The results of instructions that write to
There are 8, 64-bit branch registers (
addresses of indirect branches.
There is space for up to 128 application registers (
functions. Many of these register slots are reserved for future use. Some application
registers have assembler aliases. For example,
called
ar.ec
The instruction pointer is a 64-bit register that points to the currently executing
instruction bundle.
2.3 Using Intel
Itanium instructions are grouped into 128-bit bundles of three instructions. Each
instruction occupies the first, second, or third slot of a bundle.
expression of parallelism, and bundle specification are described below.
2.3.1

Format

A basic Itanium instruction has the following syntax:
[qp] mnemonic[.comp]
Where:
qp
mnemonic
comp
dest
srcs
2.3.2

Expressing Parallelism

The Itanium architecture requires the compiler or assembly writer to explicitly indicate
groups of instructions, called instruction groups, that have no register read after write
(RAW) or write after write (WAW) register dependencies. Instruction groups are
delimited by stops in the assembly source code. Since instruction groups have no RAW
1:140
.
®
Itanium
dest=srcs
Specifies a qualifying predicate register. The value of the qualifying
predicate determines whether the results of the instruction are committed
in hardware or discarded. When the value of the predicate register is true
(1), the instruction executes, its results are committed, and any
exceptions that occur are handled as usual. When the value is false (0),
the results are not committed and no exceptions are raised. Most Itanium
instructions can be accompanied by a qualifying predicate.
Specifies a name that uniquely identifies an Itanium instruction.
Specifies one or more instruction completers. Completers indicate optional
variations on a base instruction mnemonic. Completers follow the
mnemonic and are separated by periods.
Represents the destination operand(s), which is typically the result
value(s) produced by an instruction.
Represents the source operands. Most Itanium instructions have at least
two input source operands.
Volume 1, Part 2: Introduction to Programming for the Intel
) that control conditional execution
p0-p63
p0
are discarded.
p0
) that are used to specify the target
b0-b7
ar0-ar127
is the Epilogue Counter and is
ar66
®
Instructions
, is read-only and always
) that support various
Instruction format,
® ®
Itanium Architecture