Ia-32 Segment Register Selector Format; Ia-32 Code/Data Segment Register Descriptor Format; Ia-32 Segment Register Fields - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

EIP is added to the code segment base and zero extended into a 64-bit virtual address
on every IA-32 instruction fetch. If during an IA-32 instruction fetch, EIP exceeds the
code segment limit, a GPFault is generated on the referencing instruction. Effective
instruction addresses (sequential values or jump targets) above 4G-bytes are truncated
to 32 bits, resulting in a 4-G byte wraparound condition.
6.2.2.3 IA-32 Segment Registers
IA-32 segment selectors and descriptors are mapped to GR16 - GR29 and AR25 - AR26.
Descriptors are maintained in an unscrambled format shown in
differs from the IA-32 scrambled memory descriptor format. The unscrambled register
format is designed to support fast conversion of IA-32 segmented 16/32-bit pointers
into virtual addresses by Itanium architecture-based code. IA-32 segment register load
instructions unscramble the GDT/LDT memory format into the descriptor register
format on a segment register load. Itanium architecture-based software can also
directly load descriptor registers provided they are properly unscrambled by software.
When Itanium architecture-based software loads these registers, no data integrity
checks are performed at that time if illegal values are loaded in any fields. For a
complete definition of all bit fields and field semantics refer to the Intel
IA-32 Architectures Software Developer's Manual.
Figure 6-4.
63
TSS
Figure 6-5.
63 62 61 60 59 58 57 56 55
g d/b ig av p
Table 6-2.
Field
selector
base
lim
type
s
dpl
p
1:118

IA-32 Segment Register Selector Format

48 47
GS FS
LDT

IA-32 Code/Data Segment Register Descriptor Format

dpl s type

IA-32 Segment Register Fields

Bits
15:0 Segment Selector value, see the Intel
Developer's Manual for bit definition.
31:0 Segment Base value. This value when zero extended to 64-bits, points to the start of the
segment in the 64-bit virtual address space for IA-32 instruction set memory references.
51:32 Segment Limit. Contains the maximum effective address value within the segment for
expand up segments for IA-32 instruction set memory references. For expand down
segments, limit defines the minimum effective address within the segment. See the
®
Intel 64 and IA-32 Architectures Software Developer's Manual for details and
segment limit fault conditions. The segment limit is scaled by (lim << 12) | 0xFFF if the
segment's g-bit is 1.
55:52 Type identifier for data/code segments, including the Access bit (bit 52). See the Intel
64 and IA-32 Architectures Software Developer's Manual for encodings and
definition.
56 Non System Segment. If 1, a data segment, if 0 a system segment.
58:57 Descriptor Privilege Level. The DPL is checked for memory access permission for IA-32
instruction set memory references.
59 Segment Present bit. If 0, and a IA-32 memory reference uses this segment an
IA_32_Exception(GPFault) is generated for data segments (CS, DS, ES, FS, GS) and
an IA_32_Exception(StackFault) for SS.
Volume 1, Part 1: IA-32 Application Execution Model in an Intel
32 31
ES
SS
52 51 32 31
lim{19:0}
Description
®
64 and IA-32 Architectures Software
Figure 6-5. This format
®
64 and
16 15 0
DS
CS
base{31:0}
® ®
Itanium System Environment
GR16
GR17
0
®