Definition Of Tininess, Inexact And Underflow - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

then inexactness is signaled. If the significand was rounded by adding a one to its least
significant bit, then bit fpa in ISR.code is set to 1. Finally, an interruption due to a
Floating-Point Exception trap will occur.
Note that when rounding to single, double, or double-extended real, the overflow trap
enabled response for normal (non Parallel FP) arithmetic instructions is not guaranteed
to be in the range of a valid single, double, or double-extended real quantity, because it
is in 17-bit exponent format.
5.4.3

Definition of Tininess, Inexact and Underflow

Tininess is detected after rounding, and is said to occur when a non-zero result
(computed as though the exponent range were unbounded) would lie strictly between
Emin
+2 and -2
a tiny result may cause an exception later (such as overflow upon division because it is
so small).
Inexactness is said to occur when the result differs from what would have been
computed if both the exponent range and precision were unbounded.
How tininess and inexactness trigger the underflow exception depends on whether the
Underflow Floating-Point Exception trap is disabled or enabled. If the trap is disabled
then the underflow exception is signaled when the result is both tiny and inexact. If the
trap is enabled then the underflow exception is signaled when the result is tiny,
regardless of inexactness. Note that in the event that the Underflow Floating-Point
Exception trap is disabled and tininess but not inexactness occurs, then neither
underflow nor inexactness is signaled, and the result is a denormal.
The IEEE Underflow Floating-Point Exception trap disabled response for all normal and
Parallel-FP arithmetic instructions is to denormalize the infinitely precise result and then
round it to the destination precision. The result may be a denormal, zero, or a normal.
The inexact exception is signaled when appropriate.
The IEEE Underflow Floating-Point Exception trap enabled response for all normal
arithmetic instructions is to return the true biased exponent value MOD 2
Parallel-FP arithmetic instructions is to return the true biased exponent value MOD 2
The significand is rounded to the specified precision and written to the destination
register independent of the possibility of the exponent calculation requiring a borrow. If
the rounded value is different from the infinitely-precise value, then inexactness is
signaled. If the significand was rounded by adding a one to its least significant bit, then
bit fpa in ISR.code is set to 1. Finally, an interruption due to a Floating-Point Exception
trap will occur.
Note: When rounding to single, double, or double-extended real, the underflow trap
enabled response for normal (non Parallel FP) arithmetic instructions is not
guaranteed to be in the range of a valid single, double, or double-extended real
quantity, because it is in 17-bit exponent format.
When Flush-to-Zero mode is enabled, the behavior for tiny results is different. If an
instruction would deliver a tiny result, a correctly signed zero is delivered instead and
the appropriate FPSR.sfx.u and FPSR.sfx.i bits are set. This mode may improve the
1:106
Emin
. See Table 5-1 for the values of Emin for each real type. Creation of
Volume 1, Part 1: Floating-point Programming Model
17
and for all
8
.