Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 94

Instructions are provided to transfer between the branch registers and the general
registers. The move to branch register instruction can also optionally include branch
hints. See
Instructions are defined to transfer between the predicate register file and a general
register. These instructions operate in a "broadside" manner whereby multiple predicate
registers are transferred in parallel (predicate register N is transferred to and from bit N
of a general register). The move to predicate instruction (mov pr=) transfers a general
register to multiple predicate registers according to a mask specified by an immediate.
The mask contains one bit for each of the static predicate registers (PR 1 through PR 15
– PR 0 is hardwired to 1) and one bit for all of the rotating predicates (PR 16 through
PR63). A predicate register is written from the corresponding bit in a general register if
the corresponding mask bit is set. If the mask bit is clear then the predicate register is
not modified. The rotating predicates are transferred as if CFM.rrb.pr were zero. The
actual value in CFM.rrb.pr is ignored and remains unchanged. The move from predicate
instruction (mov =pr) transfers the entire predicate register file into a general register
target.
In addition, instructions are defined to move values between the general register file
and the user mask (mov psr.um= and mov =psr.um). The sum and rum instructions set
and reset the user mask. The user mask is the non-privileged subset of the Process
Status Register (PSR).
The mov =pmd[] instruction is defined to move from a performance monitor data (PMD)
register to a general register. If the operating system has not enabled reading of
performance monitor data registers in user level then all zeroes are returned. The mov
=cpuid[] instruction is defined to move from a processor identification register to a
general register.
The mov =ip instruction is provided for copying the current value of the instruction
pointer (IP) into a general register.
4.8 Character and Bit Strings
A small set of special instructions accelerate operations on character and bit-field data.
4.8.1 Character Strings
The compute zero index instructions (czx.l, czx.r) treat the general register source as
either eight 1-byte or four 2-byte elements and write the general register target with
the index of the first zero element found. If there are no zero elements in the source,
the target is written with a constant one higher than the largest possible index (8 for
the 1-byte form, 4 for the 2-byte form). The czx.l instruction scans the source from
left to right with the left-most element having an index of zero. The czx.r instruction
scans from right to left with the right-most element having an index of zero.
summarizes the compute zero index instructions.
Volume 1, Part 1: Application Programming Model
"Branch Prediction Hints" on page 1:78.
Table 4-33
1:83