Ia-32 Floating-Point Control Register (Fcr) - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

conditions of each IA-32 floating-point register. Itanium architecture-based code can
issue a floating-point classify operation to determine the disposition of each IA-32
floating-point register.
FCR and FSR collectively hold all IA-32 floating-point control, status and tag
information. IA-32 instructions that are updated and controlled by MXSCR, FCW, FSW
and FTAG effectively update FSR and are controlled by FSR. IA-32 reads/writes of
MXCSR, FSW, FCW and FTW return the same information as reads/writes of FSR and
FCR by Itanium instructions.
Software must ensure that FCR and FSR are properly loaded for IA-32 numeric
execution before entering the IA-32 instruction set. For Itanium instructions accessing
ignored fields, the implementation can either ignore writes and return the specified
constant on reads, or write the value and return the last value written on reads. For
Itanium instructions accessing reserved fields, the implementation can either raise
Reserved Register/Field fault on non-zero writes and return zero on reads, or write the
value (no Reserved Register/Field fault), and return the last value written on reads.
Figure 6-1.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Figure 6-2.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0 TG7 0 TG6 0 TG5 0 TG4 0 TG3 0 TG2 0 TG1 0 TG0 B C3 TOP C2 C1 C0 ES SF PE UE OE ZE DE IE
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 4443 42 41 40 39 38 37 36 35 34 33 32
Table 6-7.
IA-32 State
FSW, FTW, MXCSR state in the FSR Register
Volume 1, Part 1: IA-32 Application Execution Model in an Intel

IA-32 Floating-point Control Register (FCR)

reserved (set to 0)
reserved (set to 0)
IA-32 Floating-point Status Register (FSR)
IA-32 FTW{15:0}
reserved (set to 0)
IA-32 Floating-point Status Register Mapping (FSR)
® ®
Intel Itanium
Bits
State
11 10 9
IC RC
FZ RC PM UM OM ZM DM IM rv
IA-32 MXCSR (control)
ignored
IA-32 Usage
® ®
Itanium System Environment
IA-32 FCW{12:0}
8 7 6 5 4 3 2
PC 0 1 PM UM OM ZM DM IM
ignored
IA-32 FSW{15:0}
8 7 6 5 4 3 2
rv PE UE OE ZE DE IE
IA-32 MXCSR (status)
Usage in the Intel
®
Itanium Architecture
1 0
1 0
®
1:127