Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 139

Table 6-7.
IA-32 State
FSW.ie
FSW.de
FSW.ze
FSW.oe
FSW.ue
FSW.pe
FSW.sf
FSW.es
FSW.c3:0
FSW.top
FSW.b
FTW
zeros
MXCSR.ie
MXCSR.de
MXCSR.ze
MXCSR.oe
MXCSR.ue
MXCSR.pe
reserved
ignored
a. Exception Summary bit, see Section 6.2.2.5.4, "IA-32 Floating-point Environment" for details
b. Tag encodings indicate whether each IA-32 numeric register contains an zero, NaN, Infinity or Denormal are
not supported by reads of FSR by Itanium instructions. IA-32 instruction set reads of the FTW field do return
zero, Nan, Infinity and Denormal classifications.
c. All MMX technology instructions set all Numeric Tags to 0 = NotEmpty. However, MMX technology instruction
EMMS sets all Numeric Tags to 1 = Empty.
6.2.2.5.4
To support the Intel 8087 delayed numeric exception model, FSR, FDR and FIR contain
pending information related to the numeric exception. FDR contains the operand's
effective address and segment selector. FIR contains the numeric instruction's effective
address, code segment selector, and opcode bits. FSR summaries the type of numeric
exception in the IE, DE, ZE, OE, UE, PE, SF and ES-bits. The ES-bit summarizes the
IA-32 floating-point exception status as follows:
• When FSR.es is read by Itanium architecture-based code, the value returned is
either a summary of any unmasked pending exceptions contained in the FSR, IE,
DE, ZE, OE, UE, and PE bits or it may be the value that was last written into the
register depending on the implementation.
1:128
IA-32 Floating-point Status Register Mapping (FSR)
® ®
Intel Itanium
Bits
State
FSR.ie 0
FSR.de 1
FSR.ze 2
FSR.oe 3
FSR.ue 4
FSR.pe 5
FSR.sf 6
a
FSR.es 7
FSR.c3:0 8:10,14
FSR.top 11:13
FSR.b 15
FSR.tg 16,18,20,22
b
{7:0} ,24,26,28,30
17,19,21,23,25,
27,29,31, 39:47
FSR.ie 32
FSR.de 33
FSR.ze 34
FSR.oe 35
FSR.ue 36
FSR.pe 37
38, 48:63
39:47
IA-32 Floating-point Environment
Volume 1, Part 1: IA-32 Application Execution Model in an Intel
IA-32 Usage
Invalid operation Exception
Denormalized operand
Exception
Zero divide Exception
Overflow Exception
Underflow Exception
Precision Exception
Stack Fault
Error Summary
Numeric Condition codes
Top of IA-32 numeric stack
IA-32 FPU Busy always
equals state of FSW.ES
Numeric Tags 0-NotEmpty,
c
1-Empty
Ignored – Writes are
ignored, reads return zero
SSE Invalid operation
Exception
SSE Denormalized operand
Exception
SSE Zero divide Exception
SSE Overflow Exception
SSE Underflow Exception
SSE Precision Exception
Reserved
Ignored – Writes are
ignored, reads return zero
®
Itanium
®
Usage in the Intel
®
Itanium Architecture
None of these bits reflect
®
the status of Intel
®
Itanium floating-point
execution.
®
See the Intel 64 and
IA-32 Architectures
Software Developer's
Manual for IA-32 numeric
flag details
Does not reflect the status
® ®
of Intel Itanium
floating-point execution.
®
See Intel 64 and IA-32
Architectures Software
Developer's Manual for
details.
®
System Environment