Itanium ® Architecture - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

3.3.2.2 Data Dependency in the Intel
The Itanium architecture requires the programmer to insert stops between RAW and
WAW register dependencies to ensure correct code results. For example, in the code
below, the add instruction computes a value in r4 needed by the sub instruction:
The stop after the add instruction terminates one instruction group so that the sub
instruction can legally read r4.
On the other hand, implementations based on the Itanium architecture are required to
observe memory-based dependencies within an instruction group. In a single
instruction group, a program can contain memory-based data dependent instructions
and hardware will produce the same results as if the instructions were executed
sequentially and in program order. The pseudo-code below demonstrates a memory
dependency that will be observed by hardware:
If the address in r14 is equal to the address in r15, uni-processor hardware guarantees
that the memory location will contain the value in r17 (2). The following RAW
dependency is also legal in the same instruction group even if software is unable to
determine if r1 and r2 overlap:
3.3.2.3 Instruction Scheduling and Data Dependencies
The dependency rules are sufficient to generate correct code, but to generate efficient
code, the compiler must take into account the latencies of instructions. For example,
the generic implementation has a two cycle latency to the first level data cache. In the
code below, the stop maintains correct ordering, but a use of r2 is scheduled only one
cycle after its load:
1:150
add r4=r5,r6 ;; // Instruction group 1
sub r7=r4,r9 // Instruction group 2
mov r16=1
mov r17=2 ;;
st8 [r15]=r16
st8 [r14]=r17;;
st8 [r1]=x
ld4 y=[r2]
add r7=r6,1
add r13=r25,r27
cmp.eq p1,p2=r12,r23;;
add r11=r13,r29
ld4 r2=[r3];;
sub r4=r2,r11
® ®
Itanium Architecture
// Cycle 0
// Cycle 1
// Cycle 3
Volume 1, Part 2: Memory Reference