Ia-32 Application Register Mapping - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

• Shared: Shared registers contain values that have similar functionality in either
instruction set. For example, the stack pointer (ESP) and instruction pointer (IP)
are shared.
• Unmodified: These registers are not altered by IA-32 execution. Itanium
architecture-based code can rely on these values not being modified during IA-32
instruction set execution. The register will have the same contents when entering
the IA-32 instruction set and when exiting the IA-32 instruction set.
Table 6-1.
®
Intel Itanium
General Purpose Integer Registers
GR0
GR1-3
GR4-7
GR8
GR9
GR10
GR11
GR12
GR13
GR14
GR15
GR16{15:0}
GR16{31:16}
GR16{47:32}
GR16{63:48}
GR17{15:0}
GR17{31:16}
GR17{47:32}
GR17{63:48}
GR18-23
GR24
GR25-26
GR27
GR28
GR29
GR30
GR31
GR32-127
Process Environment
IP
Floating-point Registers
FR0
FR1
FR2-5
FR6-7
Volume 1, Part 1: IA-32 Application Execution Model in an Intel

IA-32 Application Register Mapping

®
Reg IA-32 Reg Convention
undefined
unmodified
EAX
ECX
EDX
EBX
ESP
EBP
ESI
EDI
IA-32 state
DS
ES
FS
GS
CS
SS
LDT
TSS
undefined
ESD IA-32 state
undefined
DSD
FSD
GSD IA-32 state
c
LDTD
GDTD
undefined
IP shared
unmodified
undefined
®
Size
constant 0
f
scratch for IA-32 execution
®
Intel Itanium
a
32 IA-32 general purpose registers
64 IA-32 selectors
f
scratch for IA-32 execution
64 IA-32 segment descriptors (register
b
format)
f
scratch for IA-32 execution
IA-32 segment descriptors (register
64
b
format)
d
IA-32 code execution space
64 shared IA-32 and Intel
Instruction Pointer
constant +0.0
constant +1.0
®
Intel Itanium
IA-32 code execution space
®
Itanium System Environment
Description
®
preserved registers
® ®
Itanium virtual
®
preserved registers
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