Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 115

5.4.1.3 Floating-point Exception Trap
A Floating-point Exception trap occurs if one of the following four circumstances arises:
1. The processor requests system software assistance to complete the operation, via
the Software Assist trap
2. The IEEE Overflow trap is enabled and an overflow occurs
3. The IEEE Underflow trap is enabled and an underflow occurs
4. The IEEE Inexact trap is enabled and an inexact result occurs
When an overflow, underflow, or inexact result occurs, the appropriate status flags are
updated in the FPSR. If enabled, a Floating-Point Exception trap occurs, and an
indication of which enabled trap occurred is stored in ISR.code and the fpa bit in
ISR.code (ISR{14}) is set as described in the next paragraph.
ISR.fpa is set to 1 when the magnitude of the delivered result is greater than the
magnitude of the infinitely precise result. It is set to 0 otherwise. The magnitude of the
delivered result may be greater if:
• The significand is incremented during rounding, or
• A larger pre-determined value (e.g., infinity) is substituted for the computed result
(e.g., when overflow is disabled).
There is no requirement that the Software Assist Floating-Point Exception trap ever be
signaled, nor is there a mode to force its use. In order to ensure maximum
floating-point performance, most implementations will not use this exception except in
difficult situations, such as operations creating denormal numbers. The occurrence of a
Software Assist trap is indicated when a trap bit is set in ISR.code, but that trap is
disabled. The destination register contains the trap enabled response for that trap.
The precedence among Floating-point Exception traps for arithmetic operations is
depicted in
1:104
Figure 5-12.
Volume 1, Part 1: Floating-point Programming Model