Floating-Point Memory Access Instructions - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

The trap disable (sfx.td) control bit allows one to easily set up a local IEEE exception
trap default environment. If FPSR.sfx.td is clear (enabled), the FPSR.traps bits are
used. If FPSR.sfx.td is set, the FPSR.traps bits are treated as if they are all set
(disabled). Note that FPSR.sf0.td is a reserved field which returns 0 when read.
5.3 Floating-point Instructions
This section describes the floating-point instructions. Refer to
Itanium® Instruction Set Reference
5.3.1 Memory Access Instructions
There are floating-point load and store instructions for the single, double,
double-extended floating-point real data types, and the Parallel FP or signed/unsigned
integer data type. The addressing modes for floating-point load and store instructions
are the same as for integer load and store instructions, except for floating-point load
pair instructions which can have an implicit base-register post increment. The memory
hint options for floating-point load and store instructions are the same as those for
integer load and store instructions. (See
Consistency" on page
instructions. The floating-point load pair instructions require the two target registers to
be odd/even or even/odd. See
floating-point store instructions (stfs, stfd, stfe) require the value in the
floating-point register to have the same type as the store for the format conversion to
be correct.
Table 5-7.
Operations
Single
Integer/Parallel FP
Double
Double-extended
Spill/fill
Unsuccessful speculative loads write a NaTVal into the destination register or registers
(see Section 4.4.4, "Control Speculation"). Storing a NaTVal to memory will cause a
Register NaT Consumption fault, except for the spill instruction (stf.spill).
Saving and restoring floating-point registers is accomplished by the spill and fill
instructions (stf.spill, ldf.fill) using a 16-byte memory container. These are the
only instructions that can be used for saving and restoring the actual register contents
since they do not fault on NaTVal. They save and restore all types (single, double,
double-extended, register format and integer or Parallel FP) and will ensure
compatibility with possible future architecture extensions.
Figure 5-4,
single precision, double precision, double-extended precision, integer/parallel FP, and
spill/fill data is translated during transfers between floating-point registers and
memory.
Volume 1, Part 1: Floating-point Programming Model
1:69.) Table 5-7
"ldfp — Floating-point Load Pair" on page

Floating-point Memory Access Instructions

Load to FR
ldfs
ldf8
ldfd
ldfe
ldf.fill
Figure 5-5, Figure 5-6,
for a detailed description.
Section 4.4.6, "Memory Hierarchy Control and
lists the types of floating-point load and store
Load Pair to FR
ldfps
ldfp8
ldfpd
Figure 5-7, Figure 5-8
Volume 3: Intel®
3:161. The
Store from FR
stfs
stf8
stfd
stfe
stf.spill
and Figure 5-9 describe how
1:91