Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 137

encountered in IA-32 floating-point operations, an IA-32 Exception (FPError Invalid
Operand) fault is generated.
• Floating-point values must be within the range of the IA-32 80-bit (15-bit
exponent) double extended precision format. The Itanium architecture uses 82 bits
(17-bit widest range exponent) for intermediate calculations. Software must ensure
all floating-point register values passed to IA-32 instructions are representable in
double extended precision 80-bit format, otherwise processor operation is model
specific and undefined. Undefined behavior can include but is not limited to: the
generation of an IA_32_Exception (FPError Invalid Operation) fault when used by
an IA-32 floating-point instruction, rounding of out-of-range values to
zero/denormal/infinity and possible IA_32_Exception (FPError Overflow/Underflow)
faults, or float-point register(s) containing out of range values silently converted to
QNAN or SNAN (conversion could occur during entry to the IA-32 instruction set or
on use by an IA-32 floating-point instruction). Software can ensure all passed
floating-point register values are within range by multiplying by 1.0 in double
extended precision format (with widest range exponent disabled) by using fma.sfx
fr = fr, f1, f0.
• Floating-point NaTVal values must not be propagated into IA-32 floating-point
instructions, otherwise processor operation is model specific and undefined.
Processors may silently convert floating-point register(s) containing NaTVal to a
SNAN (during entry to the IA-32 instruction set or on a consuming IA-32
floating-point instruction). Dependent IA-32 floating-point instructions that directly
or indirectly consume a propagated NaTVal register will either propagate the NaTVal
indication or generate an IA_32_Exception (FPError Invalid Operand) fault.
Whether a processor generates the fault or propagates the NaTVal is model specific.
In no case will the processor allow a NaTVal register to be used without either
propagating the NaTVal or generating an IA_32_Exception (FPError Invalid
Operand) fault.
Note: It is not possible for IA-32 code to read a NaTVal from a memory location with
an IA-32 floating-point load instruction, since a NatVal cannot be expressed by
a 80-bit double extended precision number.
It is highly recommended that floating-point values be passed on the memory stack per
typical IA-32 calling conventions to avoid numeric problems with NatVal and Itanium
denormals.
6.2.2.5.3
FPSR controls Itanium floating-point instructions control and status bits. FPSR does not
control IA-32 floating-point instructions or reflect the status of IA-32 floating-point
instructions. IA-32 floating-point and SSE instructions have separate control and status
registers, namely FCR (floating-point control register) and FSR (floating-point status
register).
FCR contains the IA-32 FCW bits and all SSE control bits as shown in
FSR contains the IA-32 floating-point status flags FSW, FTW, and SSE status fields as
shown in
floating-point register is empty. Tag encodings for zero and special conditions such as
Nan, Infinity or Denormal of each IA-32 logical floating-point register are not
supported. However, IA-32 instruction set reads of FTW compute the additional special
1:126
IA-32 Floating-point Control Registers
Figure 6-2. The Tag fields indicate whether the corresponding IA-32 logical
Volume 1, Part 1: IA-32 Application Execution Model in an Intel
Figure 6-1.
® ®
Itanium System Environment