Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 145

6.2.4.3 NaT/NaTVal Response for IA-32 Instructions
If Itanium architecture-based code sets a NaT condition in the integer registers or a
NaTVal condition in a floating-point register, MMX technology, or SSE register before
switching to the IA-32 instruction set the following conditions can arise:
• When the IA-32 instruction set is entered, NaT values must not be contained in any
register defined to contain IA-32 state, otherwise processor operation is model
specific and undefined. Processors may generate a NaT Register Consumption Abort
on any IA-32 instruction at any time (including the first IA-32 instruction) for all
IA-32 integer, MMX technology, SSE, or FP instructions regardless of whether not
that instruction directly (or indirectly) references a register containing a NaT. NaT
Register Consumption aborts encountered during IA-32 execution may terminate
IA-32 instructions in the middle of execution with architectural state already
modified.
• Floating-point NaTVal values must not be propagated into IA-32 floating-point
instructions, otherwise processor operation is model specific and undefined.
Processors may convert floating-point register(s) containing NaTVal to a SNAN
(during entry to the IA-32 instruction set or on a consuming IA-32 floating-point
instruction). Dependent IA-32 floating-point instructions that directly or indirectly
consume a propagated NaTVal register will either propagate the NaTVal indication
or generate an IA_32_Exception (FPError Invalid Operand) fault. Whether a
processor generates the fault or propagates the NaTVal is model specific. In no case
will the processor allow a NaTVal register to be used without either propagating the
NaTVal or generating an IA_32_Exception (FPError Invalid Operand) fault.
Note: It is not possible for IA-32 code to read a NaTVal from a memory location with
an IA-32 floating-point load instruction since a NaTVal cannot be expressed by
a 80-bit double extended precision number. It is highly recommended that
floating-point values be passed on the memory stack per typical IA-32 calling
conventions to avoid problems with NatVal and Itanium denormals.
• IA-32 SSE instructions that directly or indirectly consume a register containing a
NaTVal encoding, will ignore the NaTVal encoding and interpret the register's
mantissa field as a legal data value.
• IA-32 MMX technology instructions that directly or indirectly consume a register
containing a NaTVal encoding, will ignore the NaTVal encoding and interpret the
register's mantissa field as a legal data value.
Software should not rely on the behavior of NaT or NaTVal during IA-32 instruction
execution, or propagate NaT or NaTVal into IA-32 instructions.
1:134 Volume 1, Part 1: IA-32 Application Execution Model in an Intel
§
®
Itanium
®
System Environment