Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 187

By using predication to reduce the number of control flow changes, the fetching
efficiency will generally improve. The only case where predication is likely to reduce
instruction cache efficiency is when there is a large increase in the number of
instructions fetched which are subsequently predicated off. Such a situation uses
instruction cache space for instructions that compute no useful results.
4.3.4.1 Instruction Stream Alignment
For many processors, when a program branches to a new location, instruction fetching
is performed on instruction cache lines. If the target of the branch does not start on a
cache line boundary, then fetching from that target will likely not retrieve an entire
cache line. This problem can be avoided if a programmer aligns instruction groups that
cross more than one bundle so that the instruction groups do not span cache line
boundaries. However, padding all labels would cause an unacceptable increase in code
size. A more practical approach aligns only tops of loops and commonly entered basic
blocks when the first instruction group extends across more than one bundle. That is, if
both of the following conditions are true at some label L, then padding previous
instruction groups so that L is aligned on a cache line boundary is recommended:
• The label is commonly branched to from out-of-line. Examples include tops of loops
and commonly executed else clauses.
• The instruction group starting at label L extends across more than one bundle.
To illustrate, assume code at label L in the segment below is not cache-aligned and that
a cache boundary occurs between the two bundles. If a program were to branch to L,
then execution may split issue after the third add instruction even though there are no
resource oversubscriptions or stops:
L:
{ .mii
}
{ .mfb
}
On the other hand, if L were aligned on an even-numbered bundle, then all four
instructions at L could issue in one cycle.
4.4 Branch and Prefetch Hints
Branch and prefetch hints are architecturally defined to allow the compiler or hand
coder to provide extra information to the hardware. Compared to hardware, the
compiler has more time, looks at a wider instruction window (including the source), and
performs more analysis. Transfer of this knowledge to the processor can help to reduce
penalties associated with I-cache accesses and branch prediction.
1:176
add r1=r2,r3
add r4=r5,r6
add r7=r8,r9
ld8 r14=[r56] ;;
nop.f
nop.b
Volume 1, Part 2: Predication, Control Flow, and Instruction Stream