Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual page 166

3.4.3 Using Control Speculation in the Intel
Architecture
The check to determine if control speculation was successful is similar to that for data
speculation.
3.4.3.1 The NaT Bit
The Not A Thing (NaT) bit is an extra bit on each of the general registers. A register
NaT bit indicates whether the content of a register is valid. If the NaT bit is set to one,
the register contains a deferred exception token due to an earlier speculation fault. In
a floating-point register, the presence of a special value called the NaTVal signals a
deferred exception.
During a control speculative load, the NaT bit on the destination register of the load
may be set if an exception occurs and it is deferred. The exact set of events and
exceptions that cause an exception to be deferred (thus causing the NaT bit to be set),
depends in part upon operating system policy. When a speculative instruction reads a
source register that has its NaT bit set, NaT bits of the target registers of that
instruction are also set. That is, NaT bits are propagated through dependent
computations.
3.4.3.2 Control Speculation Example
When a control speculative load is scheduled, the compiler must insert a speculative
check, chk.s, along all paths on which results of the speculative load are consumed. If
a non-speculative instruction (other than a chk.s) reads a register with its NaT bit set,
a NaT consumption fault occurs, and the operating system will terminate the program.
The code sequence below illustrates a basic use of control speculation:
(p1)
This code can be rewritten using a control speculative load and check. The check can be
placed in the same basic block as the original load:
(p1)
Until a speculation check is reached dynamically, the results of the control speculative
chain of instructions cannot be stored to memory or otherwise accessed
non-speculatively without the possibility of a fault. If a speculation check is executed
and the NaT bit on the checked register is set, the processor will branch to recovery
code pointed to by the check instruction.
It is also possible to test for the presence of set NaT bits and NaTVals using the test NaT
(tnat) and floating-point class (fclass) instructions.
Volume 1, Part 2: Memory Reference
br.cond some_label
ld8 r1=[r5];;
add r2=r1,r3
ld8.s r1=[r5];;
// Other instructions
br.cond some_label
chk.s r1,recovery
add r2=r1,r3
®
// Cycle 0
// Cycle 1
// Cycle 3
// Cycle -2
// Cycle 0
// Cycle 0
// Cycle 0
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Itanium
1:155