Summary - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

will be found in
multiple of 8 and is selected by a field in the
floating-point registers can also be rotated but the number of rotating registers is not
programmable: predicate registers
registers
2.8

Summary

The Itanium architecture provides features that reduce the effects of traditional
microarchitectural performance barriers by enabling:
• Improved ILP with a large number of registers and software scheduling of
instruction groups and bundles.
• Better branch handling through predication.
• Reduced overhead for procedure calls through the register stack mechanism.
• Streamlined loop handling through hardware support of software pipelined loops.
• Support for hiding memory latency using speculation.
1:146
. The size of the rotating region of general registers can be any
r32
through are rotated.
f32 f127
Volume 1, Part 2: Introduction to Programming for the Intel
instruction. The predicate and
alloc
through are rotated, and floating-point
p16 p63
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Itanium Architecture