Ia-32 Floating-Point Register Mappings - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

Table 6-6.
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Intel Itanium
Reg
FR8
FR9
FR10
FR11
FR12
FR13
FR14
FR15
FCR (AR21)
FSR (AR28)
FIR (AR29)
FDR (AR30)
6.2.2.5.1
IA-32 floating-point registers are defined as follows:
• IA-32 numeric register stack is mapped to FR8 - FR15, using the Intel 8087 80-bit
IEEE floating-point format.
• For IA-32 instruction set references, floating-point registers are logically mapped
into FR8 - FR15 based on the IA-32 top-of-stack (TOS) pointer held in FCR.top. FR8
represents a physical register after the TOS adjustment and is not necessarily the
top of the logical floating-point register stack.
• For Itanium instruction set references, the floating-point register numbers are
physical and not a function of the numeric TOS pointer, e.g. references to FR8
always return the value in physical register FR8 regardless of the TOS value.
Itanium architecture-based software cannot necessarily assume that FR8 contains
the IA-32 logical register ST(0). It is highly recommended that typically IA-32
calling conventions be used which pass floating-point values through memory.
6.2.2.5.2
For IA-32 floating-point instructions, loading a single or double denormal results in a
normalized double-extended value placed in the target floating-point register. For
Itanium instructions, loading a single or double denormal results in an un-normalized
denormal value placed in the target floating-point register. There are two canonical
exponent values in the Itanium architecture which indicate single precision and double
precision denormals.
When transferring floating-point values from Itanium to IA-32 instructions, it is highly
recommended that typical IA-32 calling conventions be followed which pass
floating-point values through the memory stack. If software does pass floating-point
values from IA-32 to Itanium architecture-based code via the floating-point registers,
software must ensure the following:
• Single or double precision Itanium denormals must be converted into a normalized
double extended precision value expected by IA-32 instructions. Software can
convert Itanium denormals by multiplying by 1.0 in double extended precision
(fma.sfx fr = fr, f1, f0). If an illegal single or double precision denormal is
Volume 1, Part 1: IA-32 Application Execution Model in an Intel

IA-32 Floating-point Register Mappings

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IA-32 Reg
ST[(TOS + N)==0]
ST[(TOS + N)==1]
ST[(TOS + N)==2]
ST[(TOS + N)==3]
ST[(TOS + N)==4]
ST[(TOS + N)==5]
ST[(TOS + N)==6]
ST[(TOS + N)==7]
FCW, MXCSR
FSW,FTW, MXCSR
FOP, FCS, FIP
FDS, FEA
IA-32 Floating-point Stack
Special Cases
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Size (bits)
IA-32 numeric register stack
Accesses to FR8 - FR15 by Intel
80 instructions ignore the IA-32 TOS adjustment
IA-32 accesses use the TOS adjustment for a
given register N
64 IA-32 numeric and SSE control register
64 IA-32 numeric and SSE status and tag word
64 IA-32 numeric instruction pointer
48 IA-32 numeric data pointer
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Itanium System Environment
Description
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Itanium
1:125