Bundles And Templates - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

or WAW register dependencies, they can be issued without hardware checks for register
dependencies between instructions. Both of the examples below show two instruction
groups separated by stops (indicated by double semicolons):
ld8 r1=[r5] ;; // First group
add r3=r1,r4
A more complex example with multiple register flow dependencies is shown below:
ld8 r1=[r5]
sub r6=r8,r9 ;;// First group
add r3=r1,r4
st8 [r6]=r12
All instructions in a single instruction group may not necessarily issue in parallel
because specific implementations may not have sufficient resources to issue all
instructions in an instruction group.
2.3.3

Bundles and Templates

In assembly code, each 128-bit bundle is enclosed in curly braces and contains a
template specification and three instructions. Thus, a stop may be specified at the end
of any bundle or in the middle of a bundle by using one of two special template types
that implicitly include mid-bundle stops.
Each instruction in a bundle is 41-bits long. Five other bits are used by a template-type
specification. Bundle templates enable processors based on the Itanium architecture to
dispatch instructions with simple instruction decoding, and stops enable explicit
specification of parallelism.
There are five slot types (M, I, F, B, and L), six instruction types (M, I, A, F, B, L), and
12 basic template types (MII, MI_I, MLX, MMI, M_MI, MFI, MMF, MIB, MBB, BBB, MMB,
MFB). Each basic template type has two versions: one with a stop after the third slot
and one without. Instructions must be placed in slots corresponding to their instruction
types based on the template specification, except for A-type instructions that can go in
either I or M slots. For example, a template specification of
three instructions in a bundle, the first is a memory (
next two are ALU integer (
{ .mii
ld4 r28=[r8]
add r9=2,r1
add r30=1,r1
}
For readability, most code examples in this book do not specify templates or braces.
Note: Bundle boundaries have no direct correlation with instruction group boundaries
as instruction groups can extend over an arbitrary number of bundles. Instruc-
tion groups begin and end where stops are set in assembly code, and dynami-
cally whenever a branch is taken or a stop is encountered.
Volume 1, Part 2: Introduction to Programming for the Intel
// Second group
// First group
// Second group
// Second group
) or A-type instructions:
I
// Load a 4-byte value
// 2+r1 and put in r9
// 1+r1 and put in r30
®
Itanium
.MII
) or A-type instruction, and the
M
®
Architecture
means that of the
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