Floating-Point Status Register Format - Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS MANUAL VOLUME 1 REV 2.3 Manual

Table 5-2.
IA-32 Stack Double Real Denormals
(produced when computation model is
IA-32 Stack Double)
Double-Extended Real Pseudo-Denormals
(IA-32 stack and memory format)
Pseudo-Zeros
c
NaTVal
Zero
FR 0 (positive zero)
FR 1 (positive one)
a. Created by a masked real invalid operation.
b. Created by a masked integer invalid operation.
c. Created by an unsuccessful speculative memory operation.
All register encodings are allowed as inputs to arithmetic operations. The result of an
arithmetic operation is always the most normalized register format representation of
the computed value, with the exponent range limited from Emin to Emax of the
destination type, and the significand precision limited to the number of precision bits of
the destination type. Computed values, such as zeros, infinities, and NaNs that are
outside these bounds are represented by the corresponding unique register format
encoding. Double-extended real denormal results are mapped to the register format
exponent of 0x00000 (instead of 0x0C001). Unsupported encodings (Pseudo-NaNs and
Pseudo-Infinities), Pseudo-zeros and Double-extended Real Pseudo-denormals are
never produced as a result of an arithmetic operation.
Arithmetic on pseudo-zeros operates exactly as an equivalently signed zero, with one
exception. Pseudo-zero multiplied by infinity returns the correctly signed infinity instead
of an Invalid Operation Floating-Point Exception fault (and QNaN). Also, pseudo-zeros
are classified as unnormalized numbers, not zeros.
5.2 Floating-point Status Register
The Floating-Point Status Register (FPSR) contains the dynamic control and status
information for floating-point operations. There is one main set of control and status
information (FPSR.sf0), and three alternate sets (FPSR.sf1, FPSR.sf2, FPSR.sf3). The
FPSR layout is shown in
gives the FPSR's status field description and
Figure 5-2.
63
rv
6
1:88
Floating-point Register Encodings (Continued)
Class or Subclass
Figure 5-2

Floating-point Status Register Format

58 57 45 44
sf3
13
Biased
Sign
Exponent
(1 bit)
(17-bits)
0/1 0x00000
0/1 0x00000
0/1 0x00001
through
0x1FFFD
1 0x1FFFE
0 0x1FFFE
0/1 0x00000
0 0x00000
0 0x0FFFF
and its fields are defined in
Figure 5-3 shows their layout.
32 31
sf2 sf1
13 13
Volume 1, Part 1: Floating-point Programming Model
Significand
i.bb...bb
(64-bits)
(Explicit Integer Bit is Shown)
0.000...01...(11)0s
through
0.111...11...(11)0s
1.000...00 through 1.111...11
0.000...00
0.000...00
0.000...00
0.000...00
0.000...00
1.000...00
Table 5-3. Table 5-4
19 18 6 5
sf0
13
0
traps
6