Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1796

ADSP-SC58x PCIE Register Descriptions
Auxiliary Clock Frequency Control Register
The
PCIE_AUX_CLKFREQ_[n]
states with aux_clk when the PHY has removed the pipe_clk.
Figure 29-29: PCIE_AUX_CLKFREQ_[n] Register Diagram
Table 29-38: PCIE_AUX_CLKFREQ_[n] Register Fields
Bit No.
(Access)
9:0 VALUE
(R/W)
29–92
register is used to provide a 1 us reference for counting time during low-power
15 14 13
0 0 0
VALUE (R/W)
Auxiliary clock frequency in MHz
31 30 29
0 0 0
Bit Name
Auxiliary clock frequency in MHz.
The PCIE_AUX_CLKFREQ_[n].VALUE bit field is used to provide a 1 us refer-
ence for counting time during low-power states with aux_clk when the PHY has re-
moved the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of ac-
curacy in the time counted.
If the actual frequency (f ) of aux_clk does not exactly match the programmed frequen-
cy (f_prog), then an error in the time counted by the core that can be expressed in
percentage as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz and f_prog=3
MHz, then err% =(3/2.5-1)*100 =20%, meaning that the time counted by the core on
aux_clk will be 20% greater than the time in us programmed in the corresponding
time register (for example T_POWER_ON). This bit field is sticky.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
12 11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
28 27 26 25 24 23 22 21
0 0 0 0 0 0 0 0
Description/Enumeration
4 3 2 1 0
0 1 0 1 0
20 19 18 17 16
0 0 0 0 0