Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1750

PCIe Interrupts
• Vendor Defined
• Unlock Transaction (RC Mode)
• Error Signaling (EP Mode)
• Correctable
• Non-Fatal
• Fatal
• Power Management
• Event (RC Mode)
• Turn Off Acknowledge (RC Mode)
• Turn Off (EP Mode)
Configuration
Enabling interrupts that cannot be received in EP or RC modes is meaningless.
The local core or any other system cross bar master in the RC enables each specific interrupt.
• Write 1 to the appropriate interrupt enable bit in the
Interrupt Reception
Applies to the reception of an enabled interrupt. The corresponding bit in the
set. The interrupt routine should:
• Test the PCIE_APP_INTSTAT.CORERR, PCIE_APP_INTSTAT.FTLERR,
PCIE_APP_INTSTAT.NFTLERR, PCIE_APP_INTSTAT.PME PCIE_APP_INTSTAT.PMTOACK,
PCIE_APP_INTSTAT.PMTOFF, PCIE_APP_INTSTAT.UNLK, and
PCIE_APP_INTSTAT.VENDMSG bits to determine which interrupt to serve.
• Read the corresponding APP_<message name>_MSG registers (xxxMSGRQID) to discover the source of the
xxx message.
• If a Vendor message is received, reading the
PCIE_APP_VNDR_MSG_HDR0
• Once the interrupt is serviced, clear the status bit by writing 1 to the corresponding bit in the
PCIE_APP_INTSTAT
Link Up- and Receive-Overflow Interrupts
These interrupts can be enabled in both EP as well as RC modes of operation.
29–46
PCIE_APP_VNDR_MSG_HDR1
registers provide
register.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PCIE_APP_CTL register.
PCIE_APP_INTSTAT register is
and