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Application Control Register
The
PCIE_APP_CTL
interrupts are enabled.
UNLKREQ (R/W)
Generate an Unlock Message
PMOFFREQ (R/W)
Generate a PM_Turn_Off Message (RC
only)
MSIVECT (R/W)
MSI_VECTOR for Multiple Interrupt Sources
INTACLR (R/W)
Clear an EP INTA
LNKUPINTDIS (R/W)
Link UP Interrupt Disabled
RXQOVFIEN (R/W)
Receive Queues Overflow Interrupt
Enabled
PMTOFFINTEN (R/W)
Inbound Power Management Turn Off
Message Interrupt Enabled
PMACKIEN (R/W)
Inbound Power Management Ack Message
Interrupt Enabled
PMEINTEN (R/W)
Inbound Power Management Event
Message Interrupt Enabled
FERRIEN (R/W)
Inbound Fatal Error Message Interrupt
Enabled
NFTLERRINTEN (R/W)
Inbound Non Fatal Error Message Interrupt
Enabled
Figure 29-15: PCIE_APP_CTL Register Diagram
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register contains bits that control various PCIE functions. This register also reports whether
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
ADSP-SC58x PCIE Register Descriptions
LTSSMEN (R/W)
Link Training State Machine Enabled
INITDSRST (R/W)
Initiate Downstream Hot Reset
RTRYEN (R/W)
Application Retry Enable
INTREQ (R/W)
Generate an EP Interrupt
AIEN (R/W)
Legacy Interrupt A Enabled
BIEN (R/W)
Legacy Interrupt B Enabled
CIEN (R/W)
Legacy Interrupt C Enabled
DIEN (R/W)
Legacy Interrupt D Enabled
VENINTEN (R/W)
Inbound Vendor Message Interrupt
Enabled
UNLKIEN (R/W)
Inbound Unlock Message Interrupt Enabled
CORERRIEN (R/W)
Inbound Correctable Error Message
Interrupt Enabled
29–71
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