Motorola PowerQUICC II MPC8280 Series Reference Manual page 21

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11.7 Memory System Interface Example Using UPM ............................................ 11-86
11.7.0.1 EDO Interface Example........................................................................... 11-97
11.8 Handling Devices with Slow or Variable Access Times................................ 11-106
11.8.1 Hierarchical Bus Interface Example .......................................................... 11-106
11.8.2 Slow Devices Example .............................................................................. 11-106
11.9 External Master Support (60x-Compatible Mode) ........................................ 11-107
11.9.1 60x-Compatible External Masters (non-MPC8280).................................. 11-107
11.9.2 MPC8280 External Masters....................................................................... 11-107
11.9.3 Extended Controls in 60x-Compatible Mode ............................................ 11-107
11.9.4 Address Incrementing for External Bursting Masters ............................... 11-108
11.9.5 External Masters Timing............................................................................ 11-108
11.9.5.1 Example of External Master Using the SDRAM Machine ....................11-110
12.1 L2 Cache Configurations ................................................................................... 12-1
12.1.1 Copy-Back Mode........................................................................................... 12-1
12.1.2 Write-Through Mode ..................................................................................... 12-2
12.1.3 ECC/Parity Mode........................................................................................... 12-4
12.2 L2 Cache Interface Parameters .......................................................................... 12-6
12.3 System Requirements When Using the L2 Cache Interface.............................. 12-7
12.4 L2 Cache Operation ........................................................................................... 12-7
12.5 Timing Example................................................................................................. 12-8
13.1 Overview............................................................................................................ 13-1
13.2 TAP Controller................................................................................................... 13-2
13.3 Boundary Scan Register..................................................................................... 13-3
13.4 Instruction Register............................................................................................ 13-5
13.5 MPC8280 Restrictions ....................................................................................... 13-7
13.6 Nonscan Chain Operation .................................................................................. 13-7
Intended Audience ............................................................................................. IV-1
Contents ............................................................................................................. IV-1
Suggested Reading............................................................................................. IV-3
MPC82xx Documentation ......................................................................... IV-3
MOTOROLA
Freescale Semiconductor, Inc.
Contents
Title
Chapter 12
Secondary (L2) Cache Support
Chapter 13
IEEE 1149.1 Test Access Port
Part IV
Communications Processor Module
Contents
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Go to: www.freescale.com
Page
Number
xxi