Motorola PowerQUICC II MPC8280 Series Reference Manual page 13

Paragraph
Number
7.2.6.1 Data Bus Grant (DBG) .............................................................................. 7-12
7.2.6.1.1 Data Bus Grant (DBG)—Input.............................................................. 7-13
7.2.6.1.2 Data Bus Grant (DBG)—Output ........................................................... 7-13
7.2.6.2 Data Bus Busy (DBB) ............................................................................... 7-13
7.2.6.2.1 Data Bus Busy (DBB)—Output ............................................................ 7-13
7.2.6.2.2 Data Bus Busy (DBB)—Input ............................................................... 7-14
7.2.7 Data Transfer Signals..................................................................................... 7-14
7.2.7.1 Data Bus (D[0–63]) ................................................................................... 7-14
7.2.7.1.1 Data Bus (D[0–63])—Output ................................................................ 7-14
7.2.7.1.2 Data Bus (D[0–63])—Input................................................................... 7-15
7.2.7.2 Data Bus Parity (DP[0–7])......................................................................... 7-15
7.2.7.2.1 Data Bus Parity (DP[0–7])—Output ..................................................... 7-15
7.2.7.2.2 Data Bus Parity (DP[0–7])—Input ........................................................ 7-16
7.2.8 Data Transfer Termination Signals ................................................................ 7-16
7.2.8.1 Transfer Acknowledge (TA) ...................................................................... 7-16
7.2.8.1.1 Transfer Acknowledge (TA)—Input ..................................................... 7-17
7.2.8.1.2 Transfer Acknowledge (TA)—Output................................................... 7-17
7.2.8.2 Transfer Error Acknowledge (TEA).......................................................... 7-18
7.2.8.2.1 Transfer Error Acknowledge (TEA)—Input ......................................... 7-18
7.2.8.2.2 Transfer Error Acknowledge (TEA)—Output....................................... 7-18
7.2.8.3 Partial Data Valid Indication (PSDVAL) ................................................... 7-19
7.2.8.3.1 Partial Data Valid (PSDVAL)—Input.................................................... 7-19
7.2.8.3.2 Partial Data Valid (PSDVAL)—Output ................................................. 7-20
8.1 Terminology......................................................................................................... 8-1
8.2 Bus Configuration................................................................................................ 8-2
8.2.1 Single-MPC8280 Bus Mode............................................................................ 8-2
8.2.2 60x-Compatible Bus Mode.............................................................................. 8-3
8.3 60x Bus Protocol Overview ................................................................................. 8-4
8.3.1 Arbitration Phase ............................................................................................. 8-6
8.3.2 Address Pipelining and Split-Bus Transactions............................................... 8-7
8.4 Address Tenure Operations.................................................................................. 8-7
8.4.1 Address Arbitration.......................................................................................... 8-7
8.4.2 Address Pipelining........................................................................................... 8-9
8.4.3 Address Transfer Attribute Signals................................................................ 8-10
8.4.3.1 Transfer Type Signal (TT[0–4]) Encoding ................................................ 8-10
8.4.3.2 Transfer Code Signals TC[0–2] ................................................................. 8-13
8.4.3.3 TBST and TSIZ[0–3] Signals and Size of Transfer .................................. 8-13
8.4.3.4 Burst Ordering During Data Transfers ...................................................... 8-14
MOTOROLA
Freescale Semiconductor, Inc.
Contents
Title
Chapter 8
The 60x Bus
Contents
For More Information On This Product,
Go to: www.freescale.com
Page
Number
xiii