Motorola PowerQUICC II MPC8280 Series Reference Manual page 12

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Number
7.1 Signal Configuration............................................................................................ 7-2
7.2 Signal Descriptions .............................................................................................. 7-3
7.2.1 Address Bus Arbitration Signals...................................................................... 7-3
7.2.1.1 Bus Request (BR)—Output ......................................................................... 7-3
7.2.1.1.1 Address Bus Request (BR)—Output....................................................... 7-3
7.2.1.1.2 Address Bus Request (BR)—Input.......................................................... 7-4
7.2.1.2 Bus Grant (BG)............................................................................................ 7-4
7.2.1.2.1 Bus Grant (BG)—Input ........................................................................... 7-4
7.2.1.2.2 Bus Grant (BG)—Output......................................................................... 7-5
7.2.1.3 Address Bus Busy (ABB)............................................................................ 7-5
7.2.1.3.1 Address Bus Busy (ABB)—Output......................................................... 7-5
7.2.1.3.2 Address Bus Busy (ABB)—Input ........................................................... 7-6
7.2.2 Address Transfer Start Signal .......................................................................... 7-6
7.2.2.1 Transfer Start (TS) ....................................................................................... 7-6
7.2.2.1.1 Transfer Start (TS)—Output .................................................................... 7-6
7.2.2.2 Transfer Start (TS)—Input........................................................................... 7-7
7.2.3 Address Transfer Signals ................................................................................. 7-7
7.2.3.1 Address Bus (A[0–31])................................................................................ 7-7
7.2.3.1.1 Address Bus (A[0–31])—Output............................................................. 7-7
7.2.3.1.2 Address Bus (A[0–31])—Input ............................................................... 7-7
7.2.4 Address Transfer Attribute Signals.................................................................. 7-8
7.2.4.1 Transfer Type (TT[0–4]).............................................................................. 7-8
7.2.4.1.1 Transfer Type (TT[0–4])—Output........................................................... 7-8
7.2.4.1.2 Transfer Type (TT[0–4])—Input ............................................................. 7-8
7.2.4.2 Transfer Size (TSIZ[0–3]) ........................................................................... 7-8
7.2.4.3 Transfer Burst (TBST)................................................................................. 7-9
7.2.4.4 Global (GBL)............................................................................................... 7-9
7.2.4.4.1 Global (GBL)—Output............................................................................ 7-9
7.2.4.4.2 Global (GBL)—Input .............................................................................. 7-9
7.2.4.5 Caching-Inhibited (CI)—Output ............................................................... 7-10
7.2.4.6 Write-Through (WT)—Output .................................................................. 7-10
7.2.5 Address Transfer Termination Signals........................................................... 7-10
7.2.5.1 Address Acknowledge (AACK) ................................................................ 7-10
7.2.5.1.1 Address Acknowledge (AACK)—Output............................................. 7-10
7.2.5.1.2 Address Acknowledge (AACK)—Input ............................................... 7-11
7.2.5.2 Address Retry (ARTRY)............................................................................ 7-11
7.2.5.2.1 Address Retry (ARTRY)—Output ........................................................ 7-11
7.2.5.2.2 Address Retry (ARTRY)—Input ........................................................... 7-12
7.2.6 Data Bus Arbitration Signals ......................................................................... 7-12
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Freescale Semiconductor, Inc.
Contents
Title
Chapter 7
60x Signals
MPC8280 PowerQUICC II Family Reference Manual
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MOTOROLA