Functional Description Of The Spi Controller - Altera cyclone V Technical Reference

19-4

Functional Description of the SPI Controller

Signal Name
spim_ss_in_n
spim_ssi_oe_n
spim_ss_0_n
spim_ss_1_n
spim_ss_2_n
spim_ss_3_n
Table 19-4: SPI Slave Signals for FPGA Routing
spis_txd
spis_rxd
spis_ss_in_n
spis_ssi_oe_n
spis_sclk_in
Functional Description of the SPI Controller
Protocol Details and Standards Compliance
This section describes the functional operation of the SPI controller.
Altera Corporation
Signal Width
1 In
1 Out
1 Out
1 Out
1 Out
1 Out
1 Out
1 In
1 In
1 Out
1 In
Direction
Master Contention Input
Output enable for the SPI
master
Slave Select 0
Slave select signal from SPI
master
Slave Select 1
Allows second slave to be
connected to this master
Slave Select 2
Allows third slave to be
connected to this master
Slave Select 3
Allows fourth slave to be
connected to this master
Transmit data line for the SPI
slave
Receive data line for the SPI
slave
Master Contention Input
Output enable for the SPI
slave
Serial clock input
cv_5v4
2016.10.28
Description
SPI Controller
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