Slave Microwire Serial Transfers - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
• Write
• Write
• Write the
3. Enable the SPI slave by writing 1 to the
4. If the transfer mode is transmit and receive (
transmission to the master into the transmit FIFO buffer (write
( = 2), you need not write data into the transmit FIFO buffer. The current value in the transmit
TMOD
shift register is retransmitted.
5. The SPI slave is now ready for the serial transfer. The transfer begins when a serial-master device selects
the SPI slave.
6. When the transfer is underway, the
FIFO empty interrupt request is made, write the transmit FIFO buffer (write
interrupt request is made, read the receive FIFO buffer (read
7. The transfer ends when the serial master removes the select input to the SPI slave. When the transfer is
completed, the
8. If the transfer mode is not transmit only (
9. Disable the SPI slave by writing 0 to

Slave Microwire Serial Transfers

For the SPI slave, the Microwire protocol operates in much the same way as the SPI protocol. The SPI slave
does not decode the control frame.
Software Control for Slave Selection
When using software to select slave devices, the input select lines from serial slave devices is connected to
a single slave select output on the SPI master.
Example: Slave Selection Software Flow for SPI Master
1. If the SPI master is enabled, disable it by writing 0 to
2. Write
CTRLR0
3. If the transfer is receive only, write the number of frames into
4. Write
BAUDR
5. Write
TXFTLR
6. Write
IMR
7. Write
SER
8. Write
SSIENR
Example: Slave Selection Software Flow for SPI Slave
1. If the SPI slave is enabled, disable it by writing 0 to
2. Write
CTRLR0
3. Write
TXFTLR
4. Write
IMR
5. Write
SSIENR
6. If the SPI slave transmits data, write data into TX FIFO buffer.
Note: All other SPI slaves are disabled (
their
The FIFO buffer depth (
SPI Controller
Send Feedback
(for SPI transfers, set
CTRLR0
and to set FIFO buffer threshold levels.
TXFTLR RXFTLR
register to set up interrupt masks.
IMR
status is reset to 0.
BUSY
to match the required transfer.
to set the transfer baud rate.
and to set FIFO buffer threshold levels.
RXFTLR
register to set interrupt masks.
register bit 0 to 1 to select slave 1 in this example.
register bit 0 to 1 to enable SPI master.
to match the required transfer.
and to set FIFO buffer threshold levels.
RXFTLR
register to set interrupt masks.
register bit 0 to 1 to enable SPI slave.
port.
ss_in_n
) for both the RX and TX buffers in the SPI controller is 256 entries.
FIFO_DEPTH
and identical to the master device).
SCPH SCPOL
register.
SSIENR
= 0) or transmit only (
TMOD
status can be polled to return the transfer status. If a transmit
BUSY
!= 1), read the receive FIFO buffer until empty.
TMOD
.
SSIENR
.
SSIENR
.
SSIENR
= 0) and therefore will not respond to an active level on
SSIENR
Slave Microwire Serial Transfers
= 1), write data for
TMOD
). If the transfer mode is receive only
DR
). If a receive FIFO full
DR
).
DR
.
CTRLR1
19-29
Altera Corporation