Behavior - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
You can attach any I
information back and forth. There needs to be at least one master (such as a microcontroller or DSP) on
the bus and there can be multiple masters, which require them to arbitrate for ownership. Multiple masters
and arbitration are explained later in this chapter. †

Behavior

You can control the I
2
• An I C master only, communicating with other I
2
• An I C slave only, communicating with one or more I
The master is responsible for generating the clock and controlling the transfer of data. The slave is
responsible for either transmitting or receiving data to/from the master. The acknowledgement of data is
sent by the device that is receiving data, which can be either a master or a slave. As mentioned previously,
2
the I C protocol also allows multiple masters to reside on the I
determine bus ownership. †
Each slave has a unique address that is determined by the system designer. When a master wants to
communicate with a slave, the master transmits a START/RESTART condition that is then followed by the
slave's address and a control bit (R/W) to determine if the master wants to transmit data or receive data
from the slave. The slave then sends an acknowledge (ACK) pulse after the address. †
If the master (master-transmitter) is writing to the slave (slave-receiver), the receiver receives one byte of
data. This transaction continues until the master terminates the transmission with a STOP condition. If
the master is reading from a slave (master-receiver), the slave transmits (slave-transmitter) a byte of data
to the master, and the master then acknowledges the transaction with an ACK pulse. This transaction
continues until the master terminates the transmission by not acknowledging (NACK) the transaction
after the last byte is received, and then the master issues a STOP condition or addresses another slave after
issuing a RESTART condition. †
Figure 20-3: Data Transfer on the I
SDA MSB
SCL S or R
Start or Restart
Condition
2
The I C controller is a synchronous serial interface. The SDA line is a bidirectional signal and changes only
while the SCL line is low, except for STOP, START, and RESTART conditions. The output drivers are open-
drain or open-collector to perform wire-AND functions on the bus. The maximum number of devices on
the bus is limited by only the maximum capacitance specification of 400 pF. Data is transmitted in byte
packages. †
I2C Controller
Send Feedback
2
C controller to an I
2
C controller via software to be in either mode:
2
C Bus †
1 2 7
2
C-bus and every device can talk with any master, passing
2
C slaves.
2
C masters.
2
C bus and uses an arbitration procedure to
ACK
LSB
from Slave
8 9 1
Byte Complete SCL Held Low while
Interrupt within Servicing Interrupts
Slave
Behavior
ACK
from Receiver
2 3 - 8 9
Stop & Restart
Condition
Altera Corporation
20-5
P or R
R or P