Altera cyclone V Technical Reference page 2586

18-496
diepctl6
Bit
26
cnak
25:22
txfnum
21
stall
Altera Corporation
Name
A write to this bit clears the NAK bit for the endpoint.
Value
0x0
0x1
Shared FIFO Operation-non-periodic endpoints must
set this bit to zero. Periodic endpoints must map this
to the corresponding Periodic TxFIFO number. 4'h0:
Non-Periodic TxFIFO Others: Specified Periodic
TxFIFO.number An interrupt IN endpoint can be
configured as a non-periodic endpoint for applica‐
tions such as mass storage. The core treats an IN
endpoint as a non-periodic endpoint if the TxFNum
field is set to 0. Configuring an interrupt IN endpoint
as a non-periodic endpoint saves the extra periodic
FIFO area. Dedicated FIFO Operation-these bits
specify the FIFO number associated with this
endpoint. Each active IN endpoint must be
programmed to a separate FIFO number. This field is
valid only for IN endpoints.
Applies to non-control, non-isochronous IN and
OUT endpoints only. The application sets this bit to
stall all tokens from the USB host to this endpoint. If a
NAK bit, Global Non-periodic IN NAK, or Global
OUT NAK is set along with this bit, the STALL bit
takes priority. Only the application can clear this bit,
never the core. Applies to control endpoints only. The
application can only set this bit, and the core clears it,
when a SETUP token is received for this endpoint. If a
NAK bit, Global Non-periodic IN NAK, or Global
OUT NAK is set along with this bit, the STALL bit
takes priority. Irrespective of this bit's setting, the core
always responds to SETUP data packets with an ACK
handshake.
Value
0x0
0x1
Description
Description
No Clear NAK
Clear NAK
Description
STALL All Tokens not active
STALL All Tokens active
cv_5v4
2016.10.28
Access Reset
WO 0x0
RW 0x0
RO 0x0
USB 2.0 OTG Controller
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