Spi Controller Signal Description - Altera cyclone V Technical Reference

cv_5v4
2016.10.28

SPI Controller Signal Description

Signals from the two SPI masters and two SPI slaves can be routed to the FPGA or the HPS I/O pins. The
following sections describe the signals available.
Interface to HPS I/O
Table 19-1: SPI Master Interface Pins
Signal Name
CLK
MOSI
MISO
SS0
SS1
Table 19-2: SPI Slave Interface Pins
CLK
MOSI
MISO
SS0
FPGA Routing
Table 19-3: SPI Master Signals for FPGA routing:
Signal Name
spim_txd
spim_rxd
SPI Controller
Send Feedback
Signal Width Direction
1 Out
1 Out
1 In
1 Out
1 Out
1 In
1 In
1 Out
1 In
Signal Width
1
1
SPI Controller Signal Description
Description
Serial clock output from the SPI master
Transmit data line for the SPI master
Receive data line for the SPI master
Slave Select 0
Slave select signal from SPI master
Slave Select 1
Slave select signal from SPI master
Serial clock input to the SPI slave
Receive data line for the SPI slave
Transmit data line for the SPI slave
Slave select input to the SPI slave
Direction
Out
In
Description
Transmit data line for the SPI
master
Receive data line for the SPI
master
Altera Corporation
19-3