Altera cyclone V Technical Reference page 2912

Hard processor system
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18-822
doeptsiz14
Offset:
0xCD0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31
30
Reserved
rxdpid
RO 0x0
15
14
doeptsiz14 Fields
Bit
30:29
rxdpid
28:19
pktcnt
18:0
xfersize
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29
28
27
26
13
12
11
10
Name
Applies to isochronous OUT endpoints only.This is
the data PID received in the last packet for this
endpoint. Use datax. Applies to control OUT
Endpoints only. Use packetx. This field specifies the
number of back-to-back SETUP data packets the
endpoint can receive.
Value
0x0
0x1
0x2
0x3
Indicates the total number of USB packets that
constitute the Transfer Size amount of data for
endpoint 0.This field is decremented every time a
packet (maximum size or short packet) is read from
the RxFIFO.
Indicates the transfer size in bytes for endpoint 0. The
core interrupts the application only after it has
exhausted the transfer size amount of data. The
transfer size can be Set to the maximum packet size of
the endpoint, to be interrupted at the end of each
packet. The core decrements this field every time a
packet from the external memory is written to the
RxFIFO.
Bit Fields
25
24
23
22
pktcnt
RW 0x0
9
8
7
6
xfersize
RW 0x0
Description
Description
DATA0
DATA2 or 1 packet
DATA1 or 2 packets
MDATA or 3 packets
21
20
19
18
5
4
3
2
Access
USB 2.0 OTG Controller
cv_5v4
2016.10.28
17
16
xfersize
RW 0x0
1
0
Reset
RO
0x0
RW
0x0
RW
0x0
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