Altera cyclone V Technical Reference page 2575

Hard processor system

Hide thumbs Also See for cyclone V:

Table of Contents

This register indicates the status of an endpoint with respect to USB- and AHB-related events. The

application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of

the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the

application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to

get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the

appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.

Module Instance

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by

diepint5 Fields

USB 2.0 OTG Controller

Send Feedback

software or hardware. Any area of the memory map that is not explicitly defined as a register

space or accessible memory is considered reserved.

The core generates this interrupt when a NYET

response is transmitted for a non isochronous OUT

Base Address

No interrupt

NYET Interrupt

Altera Corporation

Show Quick Links

Table of Contents