Altera cyclone V Technical Reference page 3025

cv_5v4
2016.10.28
The signal transitions for the START or STOP condition, as shown in the figure, reflect those observed at
the output signals of the master driving the I
signals at the input signals of the slave(s), because unequal line delays may result in an incorrect SDA or
SCL timing relationship. †
Addressing Slave Protocol
7-Bit Address Format
During the 7-bit address format, the first seven bits (bits 7:1) of the first byte set the slave address and the
LSB bit (bit 0) is the R/W bit as shown in the following figure. When bit 0 (R/W) is set to 0, the master
writes to the slave. When bit 0 (R/W) is set to 1, the master reads from the slave. †
Figure 20-5: 7- Bit Address Format
10-Bit Address Format
During 10-bit addressing, two bytes are transferred to set the 10-bit address. The transfer of the first byte
contains the following bit definition. The first five bits (bits 7:3) notify the slaves that this is a 10-bit
transfer followed by the next two bits (bits 2:1), which set the slaves address bits 9:8, and the LSB bit (bit 0)
is the R/W bit. The second byte transferred sets bits 7:0 of the slave address. †
Figure 20-6: 10-Bit Address Format
S
S: Start Condition
R/W: Read/Write Pulse
ACK: Acknowledge (Sent by Slave)
The following table defines the special purpose and reserved first byte addresses. †
I2C Controller
Send Feedback
MSB
S A6 A5
S: Start Condition
R/W: Read/Write Pulse
ACK: Acknowledge (Sent by Slave)
1 1 1 1 0 A9
Reserved for 10-Bit Address
2
C bus. Care should be taken when observing the SDA or SCL
A4 A3 A2 A1
Slave Address
A8 A7 A6 A5 A4 A3 A2 A1 A0
R/W ACK
Addressing Slave Protocol
LSB
A0 R/W ACK
ACK
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