Spi Controller Address Map And Register Definitions - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Receive FIFO Buffer Underflow
Setting the source transaction burst length greater than the watermark level can cause underflow where
there is not enough data to service the source burst request. Therefore, the following equation must be
adhered to avoid underflow: †
DMA burst length =
If the number of data items in the receive FIFO buffer is equal to the source burst length at the time of the
burst request is made, the receive FIFO buffer may be emptied, but not underflowed, at the completion of
the burst transaction. For optimal operation, DMA burst length should be set at the watermark level,
+ 1. †
DMATDLR
Adhering to this equation reduces the number of DMA bursts in a block transfer, which in turn can
improve bus utilization. †
Note: The receive FIFO buffer will not be empty at the end of the source burst transaction if the SPI
controller has successfully received one data item or more on the serial receive line during the burst.
†
Figure 19-20: Receive FIFO Buffer
Transmit FIFO
Watermark Level
Data In

SPI Controller Address Map and Register Definitions

The address map and register definitions for the HPS-FPGA bridges consist of the following regions:
• SPI Slave Module 0
• SPI Slave Module 1
• SPI Master Module 0
• SPI Master Module 1
Related Information
Introduction to the Hard Processor System
•
The base addresses of all modules are also listed in the Introduction to the Hard Processor System
chapter.
http://www.altera.com/literature/hb/cyclone-v/hps.html
•
SPI Master Module Address Map
Registers in the SPI Master module
SPI Controller
Send Feedback
+ 1
DMATDLR
Receive
FIFO Buffer
Empty
Full
Receive FIFO Buffer Underflow
Data Out
DMARDLR + 1
on page 1-1
19-33
DMA
Controller
Altera Corporation