Altera cyclone V Technical Reference page 3003

cv_5v4
2016.10.28
txflr Fields
Bit
8:0
txtfl
rxflr
This register contains the number of valid data entriesin the receive FIFO memory. This register can be
read at any time. Ranges from 0 to 256.
Module Instance
spis0
spis1
Offset:
0x24
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
rxflr Fields
Bit
8:0
rxtfl
sr
Reports FIFO transfer status, and any transmission/reception errors that may have occurred. The status
register may be read at any time. None of the bits in this register request an interrupt.
SPI Controller
Send Feedback
Name
Contains the number of valid data entries in the
transmit FIFO.
0xFFE02000
0xFFE03000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
Contains the number of valid data entries in the
receive FIFO.
Description
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Access
Register Address
0xFFE02024
0xFFE03024
21 20 19 18
5 4 3 2
rxtfl
RO 0x0
Access
19-71
rxflr
Reset
RO 0x0
17 16
1 0
Reset
RO 0x0
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