Transfer Modes - Altera cyclone V Technical Reference

19-8
SPI Interrupts
Data are popped from the receive FIFO buffer by read commands to the SPI data register (
FIFO buffer is loaded from the receive shift register by the shift control logic. The receive FIFO buffer
generates a receive FIFO full interrupt request when the number of entries in the FIFO buffer is greater
than or equal to the FIFO buffer threshold value plus one. The threshold value, set through register
, determines the level of FIFO buffer entries at which an interrupt is generated. †
RXFTLR
The threshold value allows you to provide early indication to the processor that the receive FIFO buffer is
nearly full. A Receive FIFO Overrun Interrupt is generated when the receive shift logic attempts to load
data into a completely full receive FIFO buffer. However, the newly received data are lost. A Receive FIFO
Underflow Interrupt is generated if you attempt to read from an empty receive FIFO buffer. This alerts the
processor that the read data are invalid. †
Related Information
Reset Manager
For more information, refer to theReset Manager chapter.
SPI Interrupts
The SPI controller supports combined interrupt requests, which can be masked. The combined interrupt
request is the ORed result of all other SPI interrupts after masking. All SPI interrupts have active-high
polarity level. The SPI interrupts are described as follows: †
• Transmit FIFO Empty Interrupt – Set when the transmit FIFO buffer is equal to or below its threshold
value and requires service to prevent an underrun. The threshold value, set through a
software-programmable register, determines the level of transmit FIFO buffer entries at which an
interrupt is generated. This interrupt is cleared by hardware when data are written into the transmit
FIFO buffer, bringing it over the threshold level. †
• Transmit FIFO Overflow Interrupt – Set when a master attempts to write data into the transmit FIFO
buffer after it has been completely filled. When set, new data writes are discarded. This interrupt
remains set until you read the transmit FIFO overflow interrupt clear register (
• Receive FIFO Full Interrupt – Set when the receive FIFO buffer is equal to or above its threshold value
plus 1 and requires service to prevent an overflow. The threshold value, set through a
software-programmable register, determines the level of receive FIFO buffer entries at which an
interrupt is generated. This interrupt is cleared by hardware when data are read from the receive FIFO
buffer, bringing it below the threshold level. †
• Receive FIFO Overflow Interrupt – Set when the receive logic attempts to place data into the receive
FIFO buffer after it has been completely filled. When set, newly received data are discarded. This
interrupt remains set until you read the receive FIFO overflow interrupt clear register (
• Receive FIFO Underflow Interrupt – Set when a system bus access attempts to read from the receive
FIFO buffer when it is empty. When set, zeros are read back from the receive FIFO buffer. This
interrupt remains set until you read the receive FIFO underflow interrupt clear register (
• Combined Interrupt Request – ORed result of all the above interrupt requests after masking. To mask
this interrupt signal, you must mask all other SPI interrupt requests. †
Transmit FIFO Overflow, Transmit FIFO Empty, Receive FIFO Full, Receive FIFO Underflow, and Receive
FIFO Overflow interrupts can all be masked independently, using the Interrupt Mask Register (

Transfer Modes

When transferring data on the serial bus, the SPI controller operates one of several modes. The transfer
mode (
TMOD
Note: The transfer mode setting does not affect the duplex of the serial transfer.
Microwire transfers, which are controlled by the
Altera Corporation
on page 3-1
) is set by writing to the TMOD field in control register 0 ( ).
CTRLR0
register. †
MWCR
cv_5v4
2016.10.28
). The receive
DR
). †
TXOICR
). †
RXOICR
). †
RXUICR
). †
IMR
is ignored for
TMOD
SPI Controller
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