Spi Slave Module Address Map - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
Module Instance
spim1
Offset:
0xF0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
rx_sample_dly Fields
Bit
6:0
rsd

SPI Slave Module Address Map

Registers in the SPI Slave module
spis0
spis1
SPI Slave Module
Register
ctrlr0 on page 19-62
spienr on page 19-66
SPI Controller
Send Feedback
0xFFF01000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
This register is used to delay the sample of the rxd
input port. Each value represents a single spi_m_clk
delay on the sample of rxd. Note; If this register is
programmed with a value that exceeds 64, a 0 delay
will be applied to the receive sample. The maximum
delay is 64 spi_m_clk cycles.
Module Instance
Offset
0x0
0x8
Base Address
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
0xFFE02000
0xFFE03000
Width Acces Reset Value
s
32 RW 0x7
32 RW 0x0
SPI Slave Module Address Map
Register Address
0xFFF010F0
21 20 19 18
5 4 3 2
rsd
RW 0x0
Access
RW
Base Address
Description
Control Register 0
Enable Register
19-61
17 16
1 0
Reset
0x0
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