Sda Hold Time - Altera cyclone V Technical Reference

cv_5v4
2016.10.28
MIN_SCL_HIGHtime = 600 ns
MIN_SCL_LOWtime = 1300 ns
IC_HCNT = ceil(600 ns * 100 MHz) IC_HCNTSCL PERIOD = 60
IC_LCNT = ceil(1300 ns * 100 MHz) IC_LCNTSCL PERIOD = 130
Actual MIN_SCL_HIGHtime = 60*(1/100 MHz) = 600 ns
Actual MIN_SCL_LOWtime = 130*(1/100 MHz) = 1300 ns †

SDA Hold Time

2
The I C protocol specification requires 300 ns of hold time on the SDA signal in standard and fast speed
modes. Board delays on the SCL and SDA signals can mean that the hold time requirement is met at the
2
I C master, but not at the I
2
the I C controller contains a software programmable register,
of the SDA hold time.
DMA Controller Interface
2
The I C controller supports DMA signaling to indicate when data is ready to be read or when the transmit
FIFO needs data. This support requires 2 DMA channels, one for transmit data and one for receive data.
2
The I C controller supports both single and burst DMA transfers. System software can choose the DMA
burst mode by programming an appropriate value into the threshold registers. The recommended setting
of the FIFO threshold register value is half full.
To enable the DMA controller interface on the I
( ) bits. Writing a 1 into the
DMACR
handshaking interface. Writing a 1 into the
receive handshaking interface. †
Related Information
DMA Controller
For details about the DMA burst length microcode setup, refer to the DMA controller chapter.
Clocks
2
Each I C controller is connected to the
mode. The clock input is driven by the clock manager.
Related Information
Clock Manager
For more information, refer to Clock Manager chapter.
Resets
2
Each I C controller has a separate reset signal. The reset manager drives the signals on a cold or warm
reset.
Related Information
Reset Manager
For more information, refer to Reset Manager chapter.
I2C Controller
Send Feedback
2
C slave (or vice-versa). As each application encounters differing board delays,
effects both slave-transmitter and master mode.
IC_SDA_HOLD
bit field of
TDMAE
on page 16-1
l4_sp_clk
on page 2-1
on page 3-1
IC_SDA_HOLD
2
C controller, you must write to the DMA control register
register enables the I
DMACR
bit field of the
RDMAE DMACR
clock, which clocks transfers in standard and fast
SDA Hold Time
, to enable dynamic adjustment
2
C controller transmit
2
register enables the I C controller
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