Altera cyclone V Technical Reference page 2803

cv_5v4
2016.10.28
Bit
15
usbactep
10:0
mps
doepint6
This register indicates the status of an endpoint with respect to USB- and AHB-related events. The
application must read this register when the OUT Endpoints Interrupt bit or IN Endpoints Interrupt bit of
the Core Interrupt register (GINTSTS.OEPInt or GINTSTS.IEPInt, respectively) is set. Before the
application can read this register, it must first read the Device All Endpoints Interrupt (DAINT) register to
get the exact endpoint number for the Device Endpoint-n Interrupt register. The application must clear the
appropriate bit in this register to clear the corresponding bits in the DAINT and GINTSTS registers.
Module Instance
usb0
usb1
Offset:
0xBC8
Access:
RO
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
USB 2.0 OTG Controller
Send Feedback
Name
Indicates whether this endpoint is active in the
current configuration and interface. The core clears
this bit for all endpoints (other than EP 0) after
detecting a USB reset. After receiving the SetConfigu‐
ration and SetInterface commands, the application
must program endpoint registers accordingly and set
this bit.
Value
0x0
0x1
Applies to IN and OUT endpoints. The application
must program this field with the maximum packet
size for the current logical endpoint. This value is in
bytes.
0xFFB00000
0xFFB40000
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Description
Description
Not Active
USB Active Endpoint
Base Address
0xFFB00BC8
0xFFB40BC8
18-713
doepint6
Access Reset
RW 0x0
RW 0x0
Register Address
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