Altera cyclone V Technical Reference page 2810

18-720
doepctl7
Offset:
0xBDC
Access:
RO
31 30
15 14
doepdmab6 Fields
Bit
31:0
doepdmab6
doepctl7
Endpoint_number: 7
Module Instance
usb0
usb1
Offset:
0xBE0
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
29 28 27 26
13 12 11 10
Name
Holds the current buffer address. This register is
updated as and when the data transfer for the
corresponding end point is in progress. This register is
present only in Scatter/Gather DMA mode.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Bit Fields
25 24 23 22
doepdmab6
RO 0x0
9 8 7 6
doepdmab6
RO 0x0
Description
Base Address
0xFFB00000
0xFFB40000
21 20 19 18
5 4 3 2
Access
Register Address
0xFFB00BE0
0xFFB40BE0
USB 2.0 OTG Controller
cv_5v4
2016.10.28
17 16
1 0
Reset
RO 0x0
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