Altera cyclone V Technical Reference page 2576

Hard processor system
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18-486
diepint5
Bit
13
nakintrpt
12
bbleerr
11
pktdrpsts
9
bnaintr
8
txfifoundrn
Altera Corporation
Name
The core generates this interrupt when a NAK is
transmitted or received by the device. In case of
isochronous IN endpoints the interrupt gets
generated when a zero length packet is transmitted
due to un-availability of data in the TXFifo.
Value
0x0
0x1
The core generates this interrupt when babble is
received for the endpoint.
Value
0x0
0x1
This bit indicates to the application that an ISOC
OUT packet has been dropped. This bit does not have
an associated mask bit and does not generate an
interrupt.
Value
0x0
0x1
This bit is valid only when Scatter/Gather DMA mode
is enabled. The core generates this interrupt when the
descriptor accessed is not ready for the Core to
process, such as Host busy or DMA done
Value
0x0
0x1
Applies to IN endpoints Only. The core generates this
interrupt when it detects a transmit FIFO underrun
condition for this endpoint.
Value
0x0
0x1
Description
Description
No interrupt
NAK Interrupt
Description
No interrupt
BbleErr interrupt
Description
No interrupt
Packet Drop Status interrupt
Description
No interrupt
BNA interrupt
Description
No interrupt
Fifo Underrun interrupt
cv_5v4
2016.10.28
Access
Reset
RO
0x0
RO
0x0
RO
0x0
RO
0x0
RO
0x0
USB 2.0 OTG Controller
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