Altera cyclone V Technical Reference page 3014

19-82
dmardlr
Module Instance
spis0
spis1
Offset:
0x50
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
31 30
15 14
dmatdlr Fields
Bit
7:0
dmatdl
dmardlr
Controls DMA Receive FIFO Threshold
Module Instance
spis0
spis1
Offset:
0x54
Access:
RW
Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by
Altera Corporation
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
29 28 27 26
13 12 11 10
Reserved
Name
This bit field controls the level at which a DMA
request is made by the transmit logic. It is equal to the
watermark level; that is, the dma_tx_req signal is
generated when the number of valid data entries in
the transmit FIFO is equal to or below this field value,
and TDMAE = 1.
software or hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
Base Address
0xFFE02000
0xFFE03000
Bit Fields
25 24 23 22
Reserved
9 8 7 6
Description
Base Address
0xFFE02000
0xFFE03000
Register Address
0xFFE02050
0xFFE03050
21 20 19 18
5 4 3 2
dmatdl
RW 0x0
Access
Register Address
0xFFE02054
0xFFE03054
cv_5v4
2016.10.28
17 16
1 0
Reset
RW 0x0
SPI Controller
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