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TRACING AND DEBUGGING
Data Address
28
24
31
Figure 9-3. Data Address Breakpoint (DAB) Register Format
9.2.7.6
Instruction Breakpoint (IPB) Registers
The format for the instruction breakpoint registers is given in
(IPB) Register
Format. The upper thirty bits of the IPBx register contain the word-aligned
instruction address on which to break. The two low-order bits indicate the action to take upon an
address match.
IPBx Mode
Instruction Address
28
24
31
Figure 9-4. Instruction Breakpoint (IPB) Register Format
Programming the instruction breakpoint register modes is shown in
On the i960 Jx processor, the instruction breakpoint memory-mapped registers can be read by using
the
sysctl
instruction only. They can be modified by
9-10
20
16
12
20
16
12
Hardware Reset Value: 0000 0000H
Software Re-init Value: 0000 0000H
sysctl
or by a word-length store instruction.
8
4
0
Hardware Reset Value: 0000 0000H
Software Re-init Value: 0000 0000H
Figure 9-4. Instruction Breakpoint
m
m
1
0
8
4
0
Table 9-4
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